Integrated tuner

ABSTRACT

An integrated tuner comprises a step AGC amplifier ( 1 ) that is adjusted only during a vertical synchronization interval. A receiver comprises such an integrated tuner and an IF demodulation circuit ( 5,6 ) for providing a vertical sync signal to the integrated tuner.

This application is a national stage of PCT/IB2004/050306 having aninternational filing date of Mar. 22, 2004 and claims priority from EPapplication 0320802.2 filed Mar. 28, 2003, the contents of which arehereby incorporated by reference in its entirety.

The invention relates to an integrated tuner having an automatic gaincontrol (AGC) circuit, and to a receiver comprising such an integratedtuner.

Tuners for TV or data reception have AGC circuitry to handle inputsignals with different levels, which can change during time. Variablegain stages are commonly used in tuners. These circuits are applied inthe RF domain and IF domain as well. To have the best signal to noiseratio at the output of the tuner, the AGC preamplifier stage in thetuner should have a well-defined gain at every input signal level. Veryoften the gain setting is a trade off between noise and distortionwithin the limits of the specification of the specific application.

Normally in TV tuners continuous AGC circuitry is used. In case of gainchanges no influences on the screen can be seen. Continuous AGCcircuitry is always equipped with a MOSFET. There is of course aneconomic reason to integrate this AGC function into the mixer/oscillatorIC of the tuner. When integrated, a continuous AGC circuitry using aGilbert cell causes undesired noise and intermodulation during automaticgain control.

It is, inter alia, an object of the invention to provide an improvedintegrated tuner. To this end, the invention provides a tuner as definedin the independent claims. Advantageous embodiments are defined in thedependent claims.

In accordance with the present invention, an integrated tuner comprisesa step AGC amplifier that is adjusted only during a verticalsynchronization interval. A receiver comprises such an integrated tunerand an IF demodulation circuit for providing a vertical sync signal tothe integrated tuner. Advantageously, in a step AGC amplifier usingresistors in feedforward and feedback paths around an operationalamplifier structure, at large input signals amplification is reduced andfeedback is increased, which results in a good intermodulation distance.

These and other aspects of the invention will be apparent from andelucidated with reference to the embodiments described hereinafter.

IN THE DRAWINGS

FIG. 1 shows an embodiment of a step AGC amplifier; and

FIG. 2 shows an embodiment of a receiver comprising a tuner inaccordance with the present invention.

In this invention, a step AGC amplifier 1 is used. The several gainsettings are realized by choosing the ratio of resistors in a circuitwith an inverting amplifier. See FIG. 1. The AGC amplifier 1 is situatedat an input of a tuner. By means of an AGC detector 9 the gain should beadjusted such that no overloading or too much intermodulation willoccur. The picture quality is suffering strongly during gain changes dueto the fact that the AGC amplifier 1 in the tuner has discrete steps. Tohave no visible interference in the picture, the gain changes should beoutside the visible area on the TV screen. In this proposal there ischosen for AGC steps during the vertical synchronization period. Anembodiment of the invention as described in FIG. 2 also includes asolution to define the number of steps during the verticalsynchronization interval.

In FIG. 2, variable gain amplifier 1 has discrete gain steps. The gainvariation can be e.g. 0.1, 0.5 or 1 dB per step. The gain can be madee.g. by a ratio of resistors. When switching between resistors, the gainwill change. Controllable selectivity filter 2 provides selectivity inthe tuner to suppress unwanted frequencies such as image frequencies andsignals with high levels. A mixer 3 shifts the wanted signal to anIntermediate Frequency (IF) which could be e.g. 38.9, 45.75, 56.75 MHz.The mixer 3 will be driven by an oscillator, which is not drawn in theblock diagram. The principle proposed is not exclusive for standard IF.It is also applicable for up-conversion or conversion to low or zero IF.A SAW filter 4 provides channel selectivity. This filter 4 is necessaryto suppress neighbor channels and this filter makes a Nyquist slope forproper demodulation of analog TV signals. For low or zero IF other kindof filters are used. An IF demodulator 5 demodulates the IF signal tobase-band CVBS signal. The IF demodulator 5 has an internal AGCcircuitry to handle different IF input levels with a constant CVBSoutput level of 1 Vpp. Alternatively, a digital IF demodulator foranalog transmissions can be used. A synchronization slicer 6 separatesthe vertical synchronization pulse v-sync from the CVBS signal. Thisslicer 6 can be made of a so-called H/V PLL circuitry, which locks onthe synchronization signals of the CVBS signal. In this proposal, thepulse width of the v-sync is adjustable, for which purpose the slicer 6receives a pulse width adjustment signal PWA. A clock generator 7 isused for the up-down counter. The frequency of the clock generator willcontrol the number of AGC steps during the pulse width of the v-syncsignal. Therefore the gate connects the clock generator 7 with up-downcounter 11 only during the pulse width of the vertical synchronizationpulse. A level detector 9 measures the level of the output of the AGCamplifier 1. The detector 9 could be a RMS or peak detector. Low passfiltering is made by the use of capacitor C1. That means that thevoltage on C1 is always a reflection of the total output level of theAGC amplifier 1. A dual comparator 10 measures the voltage across acapacitor C1. It has three ranges: too low, too high and a range in themiddle. It decides whether the voltage, which is a reflection of theinput level, of the capacitor C1 is to high, to low or in the middle.The outputs “up” and “down” will control the direction of the counter 11when the clock is active. An up-down counter 10 controls the switches inthe AGC amplifier 1. The counter counts up or down depending on theoutput of the dual comparator 10. It counts when the clock signal isreceived from the clock generator via the gate. IF demodulator 5 andsync slicer 6 may be in an IF IC, while the other items shown in FIG. 2may be in a tuner IC.

The AGC amplifier 1 amplifies the total signal from an antenna input.The selectivity filter 2 filters out the wanted channel and has tosuppress unwanted channels such as image frequency and strong far awaychannels. The output signal is mixed to IF and filtered by the channelfilter 4. The output signal is then demodulated by the IF demodulator 5.The output signal of the IF demodulator 5 is the CVBS signal. Thesynchronization slicer 6 separates the vertical synchronization signalfrom this CVBS signal. The width of the vertical synchronization pulseat the output of the slicer 6 can be adjusted to control the number ofclock pulses going from the clock generator 7 to the up-down counter 11.That means that only during the vertical synchronization output pulseperiod of the sync slicer 6, the AGC amplifier 1 can change a certainnumber of steps. The number of steps can be controlled by e.g. an I2Cbus via setting of the pulse width or frequency of the clock generator7. With this adjustment a customer can influence the speed of AGC changeor the extent of interference caused by gain changes.

In this preferred embodiment of the AGC system, in contradistinction toother AGC systems in TV where the input signal of the level detector isgated, the detector should work continuously to measure a total power ofall signals in all channels applied to the AGC amplifier 1, whileadjustment is only done during the vertical synchronization interval tohave no visible interference in the picture. At capacitor C1 always thedetected voltage is present and will reflect the output level of the AGCamplifier. The dual comparator 10 has always the information whether theoutput voltage of the AGC amplifier 1 is too high, too low or in themiddle. That means that the counter 11 should count up, down or therewill be no change. This will happen when the clock signal is active atthe input of the up-down counter.

The invention provides the following advantages. Solution on systemlevel to avoid disturbances in the TV picture during step AGC.Flexibility to change the number of steps during verticalsynchronization interval. Due to the given solution, now it is possibleto integrate the AGC function into an IC for tuner application.

It should be noted that the above-mentioned embodiments illustraterather than limit the invention, and that those skilled in the art willbe able to design many alternative embodiments without departing fromthe scope of the appended claims. In the claims, any reference signsplaced between parentheses shall not be construed as limiting the claim.The word “comprising” does not exclude the presence of elements or stepsother than those listed in a claim. The word “a” or “an” preceding anelement does not exclude the presence of a plurality of such elements.The invention may be implemented by means of hardware comprising severaldistinct elements, and by means of a suitably programmed computer. Inthe device claim enumerating several means, several of these means maybe embodied by one and the same item of hardware. The mere fact thatcertain measures are recited in mutually different dependent claims doesnot indicate that a combination of these measures cannot be used toadvantage.

1. An integrated tuner comprising: a step Automatic Gain Control (AGC)amplifier; and means for adjusting the step AGC amplifier (1) onlyduring a vertical synchronization interval, wherein the adjusting meanscomprise: a clock generator for generating clock pulses; an up/downcounter for generating control signals to adjust the step AGC amplifier;means for passing said clock pulses to said up/down counter only duringsaid vertical synchronization interval.
 2. An integrated tuner asclaimed in claim 1, wherein the adjusting means further comprise: alevel detector coupled to an output of the step AGC amplifier; and adual comparator coupled to an output of said level detector to provideup/down control signals to said up/down counter in dependence on anoutput signal of said level detector.
 3. An integrated tuner as claimedin claim 2, wherein the level detector continuously measures a totalpower of all signals in all channels applied to the step AGC amplifier.4. An integrated tuner comprising: a step Automatic Gain Control (AGC)amplifier; a synchronization slicer for separating a verticalsynchronization signal from a Composite Video Broadcast Signal (CVBS)signal; means for adjusting the step AGC amplifier only during avertical synchronization interval output pulse period of thesynchronization slicer; wherein a width of the vertical synchronizationsignal output from the synchronization slicer is adjusted to control anumber of pulses output to the means for adjusting the AGC amplifier. 5.An integrated tuner as claimed in claim 4, wherein the adjusting meanscomprise: a clock generator for generating clock pulses; an up/downcounter for generating control signals to adjust the step AGC amplifier;means for passing said clock pulses to said up/down counter only duringsaid vertical synchronization interval.
 6. An integrated tuner asclaimed in claim 5, wherein the adjusting means further comprise: alevel detector coupled to an output of the step AGC amplifier; and adual comparator coupled to an output of said level detector to provideup/down control signals to said up/down counter in dependence on anoutput signal of said level detector.
 7. An integrated tuner as claimedin claim 6, wherein the level detector continuously measures a totalpower of all signals in all channels applied to the step AGC amplifier.8. A receiver comprising: an integrated tuner as claimed in claim 4; andan IF demodulation circuit for providing a vertical sync signal to theintegrated tuner.